中史地_2 — 疆域变迁与边疆问题

CS61c_8 — Control logic and lab05

中史地_1 — 中国历史地理疆域变迁

CS61c_7 — RISC-V Processor Design

CS61c_6 — Combinational Logic Blocks

CS61c_5 — Intro to Synchronous Digital Systems

CS61c_4 — Compilation,Assembly,Linking and Loading

CS61c_3 — Instruction formats

FPGA2 — 基于FPGA的串口发送实验以及verilog实现

CS61c_2 — RISC-V procedures and Lab3

FPGA1 — 阻塞赋值与非阻塞赋值

CS61c_1 — RISC-V lw,sw,Decisions I,II and Lab2

CS61c_0 — RISC-V intro and Project 1

FPGA0 — 可控线性序列机

A Simple Wordcloud with Python